Advances in semiconductor chip fabrication and packaging technologies have enabled the development of highly integrated semiconductor chips and compact chip package structures or electronic modules. For example, silicon integrated circuit chips can be fabricated with high integration density and functionality to form what is referred to as SoC (System on Chip). With SoC designs, the functionality of a complete system (e.g., computer) is integrated on a single silicon die. SoC solutions may not be practical or achievable for chip-level integration when a given system design requires the use of heterogeneous semiconductor technologies to fabricate the necessary system integrated circuits.
In this regard, SIP (System In a Package) or SOP (System On a Package) techniques are used to integrate various die technologies (e.g., Si, GaAs, SiGe, SOI) to form a complete system which approximates SoC performance. By way of example, a SOP module can be constructed by mounting a plurality of semiconductor chips to a chip carrier substrate having conductive through-vias (and other conductive wiring) which provide I/O and power interconnects between IC chips on the top-side of the carrier and I/O contacts on a next level packaging structure coupled to the bottom-side of the carrier. Depending on the application, SOP modules can foe constructed using ceramic, organic, or semiconductor carrier structures.
Conventional packaging solutions have been based primarily on organic and ceramic carrier technologies. There are disadvantages associated with organic and ceramic carrier technologies including, for example, high fabrication costs and inherent limitations the practical integration, density, I/O density, power density, etc, that may be achieved using organic or ceramic carriers, as is known in the art. It is believed that inherent limitations and high fabrication costs associated with ceramic and organic carrier technologies may limit the ability or desire to use such carrier technologies to meet the increasing demands for higher density and higher performance packaging solutions.
On the other hand, there has been increasing focus on the use of silicon carrier technologies to support the next generation packaging solutions. Indeed, state of the art silicon manufacturing techniques which follow CMOS back-end-of line design rules can be employed for low-cost fabrication of silicon carriers having high density wiring and through-via interconnects, sufficient to support enabling low-cost and high-density I/O SOP packaging solutions. One significant advantage in using silicon carrier packages for high density packaging of silicon chips, for example, is that both carrier and chip have the same or similar CTE (coefficient of thermal expansion). In this regard, during thermal cycling, the expansion and contraction between the silicon carrier packages and silicon chips is matched, thereby minimizing the stresses and strains that may be generated in the contacts (e.g., solder balls) between chip and substrate, thereby allowing high-density micro bump interconnections to scale to smaller sizes.
Despite the increasing focus in the microelectronics industry on the use of silicon carrier substrates for packaging designs, fabrication of silicon carriers with conductive through-vias for high-performance applications is not trivial. In general, silicon carriers with thru wafer via interconnects are fabricated using various techniques that generally include processing steps such as forming via holes in silicon substrates by mechanical drilling or using damascene type process flows including patterning and then wet etching or dry etching, depositing liner/seed layers on the via hole sidewalls, via metallization to fill the via holes with a metallic material (deposition or electroplating), and chemical mechanical polishing (CMP).
The ability to fabricate silicon carriers with high yield and low defect density can be problematic using conventional methods depending on, e.g., the size and geometry of the target vias (aspect ratio, width, pitch), the types of materials and/or processes used to line and fill the via holes, and the order of the processing steps, etc. For example, due to the CTE mismatch between the silicon substrate and the liner/insulation and metallic materials (e.g., copper, tungsten) used to fill the vias, substantial stresses and strains may be generated at the via sidewalls clue to differences in thermal expansion and contraction during carrier substrate production and via processing, which can result in interfacial delamination at the via sidewalls and/or cracking or fracturing of the silicon substrate. These thermal-mechanical defects can occur, for example, when forming via diameters of 1˜10 microns for vertical thickness of less than 10 microns. Therefore, differential thermal expansion of the materials forming the through-via structures and the substrate material during via manufacturing is a critical design issue.
Moreover, the ability to form high aspect ratio through-vias (e.g., copper through-vias with aspect rations of greater than 30 to 1) is challenging to form defect free vias due to common problems such as pinch off and/or process chemical entrapment in the resulting via structure (e.g., entrapment of electrolyte during electroplating), etc
Some conventional methods include vias that are fabricated by forming a closed end vertical hole lined with insulation and filled with a conductive inner core, followed by thinning and removal of the underlying substrate material and dielectric insulator at the bottom of the vias to open electrical contact to the conductor. Defect free filling of the closed end vias and control and uniformity later thinning the wafer to open is dependent on targeted feature sizes and process tolerance control. Therefore, depending on the desired structure (via diameter, height), wafer processing and tolerance controls, the impact on manufacturing yield can be significant.